Memory circuits are often used as buffers to store data for and from various input/output (I/O) devices such as terminals, printers or modems. These memories are often accessed by multiple processors. However, in order to prevent erroneous address, data or control signals, access to the memory must be controlled, such that only one processor has access to the memory at any particular time.
Such memory access control typically requires complex timing and logic circuitry.
Accordingly, it is the object of the present invention to provide a novel memory access selection circuit which does not utilize complex timing and logic circuitry.